1. Field of the Invention
The present invention relates to a method of fabricating a buried contact structure used in MOS and bipolar (including BiMOS or BiCMOS) semiconductor devices, and more particularly to a method of fabricating a buried contact structure by forming a silicide layer on the sidewall of the interconnect layer of the semiconductor devices to make electrical contact with the source/drain regions.
2. Description of the Related Art
Buried contacts have been extensively used in MOS memory integrated circuits. For example, buried contacts are used in a MOS SRAM (static random-access memory) cell, which employs two loads (active load or passive load) and two cross-coupled MOS transistors, to connect each gate electrode to the drain region of the opposing cross-coupled MOS transistors. In a typical memory cell architecture, the buried contacts are also electrically connected to source/drain regions of MOS transistors, which form transmission-gates to provide data path into or out of the memory cell. Consequently, buried contacts provide electrical interconnection among gate electrodes, drain regions of the cross-coupled MOS transistors and source/drain regions of the transmission-gate transistors.
A conventional process for the formation of buried contacts is illustrated in FIGS. 1A through 1F. First referring to FIG. 1A, field oxide 100 is first formed on P-type semiconductor substrate 1, such as the LOCOS (local oxide of silicon) method. Field oxide 100 serves as an isolation layer. Then, a gate oxide layer 10 is formed over the surface of the substrate 1 not covered by field oxide 100. First polysilicon layer 12A is then deposited on field oxide 100 and gate oxide layer 10.
Referring next to FIG. 1B, first polysilicon layer 12A and gate oxide layer 10 are then patterned and etched to form opening 102 to expose a portion of substrate 1.
Referring to FIG. 1C, second polysilicon layer 12B is then conformably deposited over exposed substrate 1 at opening 102 and first polysilicon layer 12A.
Referring to FIG. 1C and FIG. 1D, second polysilicon layer 12B and first polysilicon layer 12A are thereafter patterned and etched to define transistor gate electrode 13 and interconnect layer 12. Note that trench 104 will be inevitably formed in substrate 1 during the etching process used to define gate electrode 13 and interconnect layer 12. It is noted that the ratio of etch rates of different materials is known as the selectivity of an etch process. Since there is poor substrate/polysilicon etch selectivity, no gate oxide layer 10 is provided within the region of opening 102 as an etching stop, and the reactive ion etch gases used to etch polysilicon layers 12A and 12B also etch the single crystal silicon substrate 1 at about the same rate. After that, thin oxide layer 106 with a thickness of 50-500.ANG. is formed on all of the surface to serve as a passivation layer during the subsequent implantation process. Then, a N-type ion implantation is applied to create N-type lightly-doped region 14 in substrate 1.
Referring now to FIG. 1E, by chemical vapor deposition, a CVD oxide layer is deposited onto the overall surface and combines with the thin oxide layer 106 to form a oxide layer 108. The thickness of CVD oxide layer is about 2500.ANG. to 3000.ANG..
Finally, referring to FIG. 1F, oxide layer 108 is then removed by etch back process. Note that spacers 108 remain on the side walls of gate electrode 13 and interconnect layer 12 after the etch back process. Next, another N-type ion implantation, which uses a higher implantation dose than that used for forming lightly-doped region 14, is applied to form N-type heavily-doped region 16 in substrate 1 to finish the process. The resulting structure as depicted in FIG. 1F is a conventional buried contact structure, wherein the marked area 107 is a contact region.
However, the conventional buried contact structure makes use of the interconnect layer 12 extending over the a portion of the N-type heavily-doped region 16 to make electrical contact through the contact region 107. This become a disadvantage in the scaling down of dimensions of semiconductor devices. The complicated process for the formation of a buried contact structure is another problem. Moreover, the inevitably formed trench 104 will make spacer 108 within opening 102 become thicker, thus reducing the dosage of impurities implanted in the underlying heavily-doped region 16. This accordingly increases the resistance and thus induces the resistance deviation of the heavily-doped region 16. Trench 104 will also result in poor step coverage in the subsequent process steps, for example in the deposition of pre-metal dielectric layer such as BPSG (borophosphosilicate glass), thus reducing the reliability of the resulting semiconductor devices.